Multilayered printed wiring board

ABSTRACT

Multilayer printed wiring board capable of effectively solving the swelling of the conductor layer resulting from residual solvent and lowering of adhesion property between a resin insulating layer and a conductor. The multilayer printed wiring board can be formed by laminating resin insulating layers and conductor layers on a substrate, wherein, among conductor layers at least constituted with signal layer and power layer, a conductor pattern of the power layer is of lattice-shaped form.

TECHNICAL FIELD

This invention relates to a multilayer printed wiring board, and moreparticularly it proposes a multilayer printed wiring board characterizedby having a conductor pattern of a power layer arranged for supplying acurrent to a signal layer.

BACKGROUND ART

In a multilayer printed wiring board formed by laminating interlaminarinsulating layers and conductor layers, the conductor layers are dividedinto a power layer, a signal layer and a shield layer in accordance withuse purpose and functioned individually. Among them, the power layer isusual to be a flat conductor pattern having a large surface area.

On the other hand, the multilayer printed wiring board is producedthrough an additive process by alternately building up a resininsulating layer and a conductor layer on a substrate and thenelectrically connecting the conductor layers to each other through aviahole formed in the resin insulating layer. In the production processof such a multilayer printed wiring board, therefore, there is atendency that a solvent is liable to be retained in the interlaminarinsulating layer disposed on a lower side of the conductor layer.

For example, when an air permeable resin layer such as a resist isformed on the interlaminar insulating layer, such a residual solvent isevaporated and removed by a heat treatment such as a drying treatmentconducted at a plating step or the like, so that such a solvent does notparticularly cause a problem.

However, when an impermeable metal layer such as a conductor layer isformed on the interlaminar insulating layer, it is very difficult toremove the above residual solvent by evaporation. Particularly, when thepower layer having a flat pattern as a conductor pattern among theconductor layers is formed on the resin insulating layer throughadditive process, the residual solvent is retained between the powerlayer and the resin insulating layer as a vapor and there is a problemeasily causing so-called “swelling of conductor layer”.

Further, such a “swelling of conductor layer” degrades the adhesionproperty between the resin insulating layer and the conductor and hencecauses the lowering of the interlaminar insulating property.

It is, therefore, an object of the invention to provide a multilayerprinted wiring board capable of solving the above problems resultingfrom the residual solvent, and to particularly propose a conductorpattern of a power layer capable of preventing the swelling of theconductor layer and effectively acting to improve the adhesion propertybetween the resin insulating layer and the conductor.

SUMMARY OF THE INVENTION

The inventors have made various studies in order to achieve the aboveobject and as a result the present invention relates to a multilayerprinted wiring board formed by laminating resin insulating layers andconductor layers on a substrate, wherein the surface of the resininsulating layer is roughened and among conductor layers at leastconstituted with signal layer and power layer, a conductor pattern ofthe power layer is of lattice-shaped form.

In the above multilayer printed wiring board, the power layer isdesirable to have such a conductor pattern that a conductor width of thelattice-shaped conductor is 100 μm˜5 mm and a distance between theconductor is 100 μm˜10 mm.

Also, the conductor pattern of the power layer in the multilayer printedwiring board is desirable that each corner part in a cross portion ofthe lattice-shaped conductor is curved.

Moreover, the resin insulating layer constituting the multilayer printedwiring board according to the invention is desirable to be formed bydispersing heat-resistant resin particles soluble in an acid or anoxidizing agent into a heat-resistant resin (or a photosensitive resin)hardly soluble in an acid or an oxidizing agent. The surface of such aresin insulating agent is roughened by removing the heat-resistant resinparticles with the acid or oxidizing agent. On the other hand, when thelattice-shaped power layer is formed, the plated resist is an isolatedshape surrounded with the conductors and is liable to be peeled off asit is. In this point, when the plated resist is formed on the aboveroughened surface, the plated resist hardly peels off even in theisolated shape and hence the reliability is ensured.

In one aspect, the present invention is directed to a multilayer printedwiring board comprising a substrate; at least one resin insulating layerand at least one conductor layer laminated on the substrate; the atleast one resin insulating layer comprising a roughened surface; the atleast one conductor layer comprising at least a signal layer and a powerlayer; and the power layer comprising a lattice-shaped conductor patternincluding a conductor width of about 100 μm to 5 mm, and a distance froma conductor edge to an opposing conductor edge of about 100 μm to 10 mm.

Each corner part in a cross portion of the lattice-shaped conductorpattern can be curved.

The at least one resin insulating layer and the at least one conductorlayer can comprise a plurality of insulating layers and conductorlayers.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1A to 1E are schematic views illustrating steps of forming a powerlayer in a multilayer printed wiring board according to the presentinvention; and

FIGS. 2A-2D are schematic views illustrating steps of forming a powerlayer in a conventional multilayer printed wiring board.

In this case, numeral 1 is a substrate, numeral 2 an interlaminarinsulating layer, numeral 3 a permanent resist plated resist), andnumeral 4 a power layer.

BEST MODE FOR CARRYING OUT THE INVENTION

The multilayer printed wiring board according to the invention lies in apoint that the pattern of the conductor formed as a power layer amongthe conductor layers is not a full form (flat form) but is alattice-shaped form. Thus, the solvent retained in the resin layerbeneath the power layer is naturally removed from a resin portion thatis a portion not forming the conductor of the power layer (between thelattice-shaped patterns), so that it is not retained beneath the powerlayer as it is. As a result the swelling is not caused in the powerlayer having the above structure, and the adhesion property of the powerlayer to the lower-side resin insulating layer is improved.

In the conventional power layer made from full conductor (flat pattern),when the resin insulating layer is formed on the conductor, it isnecessary that at least a surface of the conductor is subjected to aroughening treatment in order to ensure the adhesion property betweenbetween the conductor and the resin insulating layer. In thisconnection, in the power layer provided with the lattice-shapedconductor pattern according to the invention, the resin layer isexistent on a portion of the power layer not forming the conductor(between the lattice-shaped conductor patterns), so that at least asurface of this portion is not necessary to be subjected to theroughening treatment and hence it is joined to an upper-side resininsulating layer through the resin. The joint between resin and resin(same kind) is superior to the joint between resin and metal (differentkind) in the adhesion property. Further, the power layer has a structureof unevenly repeating the resin portion and the lattice-shaped conductorportion and is joined to the upper-side resin insulating layer at anuneven fitted state, so that the joint strength becomes considerablyhigh. As a result, the adhesion property between the power layer and theupper-side resin insulating layer in the multilayer printed wiring boardaccording to the invention is considerably improved.

In such a multilayer printed wiring board according to the invention, itis desirable that the conductor pattern of the power layer has aconductor width of the lattice-shaped conductors of 100 μm˜5 mm and adistance between the conductors of 100 μm˜10 mm. Because, when they areless than 100 μm, the pattern formation is very difficult from aviewpoint of the production limitation. On the other hand, when theconductor width exceeds 5 mm, the residual solvent in the resin layerbeneath the conductor is hardly removed, and when the conductor distanceexceeds 10 mm, the area of the conductor serving as the power isconsiderably decreased, so that the electric properties of the powerlayer are degraded.

And also, the conductor pattern of the power layer is desirable thateach corner part in a cross portion of the lattice-shaped conductor iscurved. That is, it is desirable that each cross connecting portion issubjected to a round treatment short-cutting into a circle or anellipsoid, Because, stress concentration (particularly produced in heatcycle) into the resin layer existing in the portion not forming theconductor of the power layer (between the lattice-shaped conductorpatterns) or the plated resist (permanent resist) is prevented by such around treatment and the occurrence of cracks in the resist can beprevented.

The conductor pattern of the power layer constituting the multilayerprinted wiring board according to the invention is concretely describedwith reference to examples below.

EXAMPLES Example 1

In this example, the power layer constituting the multilayer printedwiring board is formed as follows.

At first, an interlaminar insulating layer 2 made of a heat-resistantresin (PES) is formed on a substrate 1 and the surface of theinterlaminar insulating layer 2 is roughened with a solution ofpermanganate to a roughness of Rz=6 μm according to JIS-B0601 (see FIG.1(A)). Moreover, the interlaminar insulating layer 2 after theroughening has a thickness of 35 μm.

Then, a desired permanent resist (made of epoxy resin) 3 correspondingto the conductor pattern of the power layer is pattern-printed onto thesurface of the interlaminar insulating layer (see FIG. 1(B)), andsubjected to an electroless copper plating to form a power layer 4having a lattice-shaped conductor pattern (see FIG. 1(C)). The latticestructure of the power layer 4 is conductor width/resist width=250μm/250 μm in both directions of X-axis and Y-axis.

Example 2

In this example, the power layer constituting the multilayer printedwiring board is formed as follows.

At first, an interlaminar insulating layer 2 made of a heat-resistantresin (PES- epoxy resin) is formed on a substrate 1 and the surface ofthe interlaminar insulating layer 2 is roughened with a solution ofpermanganate to a roughness of Rz=6 μm according to JIS-B0601 (see FIG.1(A)). Moreover, the interlaminar insulating layer 2 after theroughening has a thickness of 35 μm.

Then, a desired permanent resist (made of epoxy resin) 3 correspondingto the conductor pattern of the power layer is pattern-printed onto thesurface of the interlaminar insulating layer (see FIG. 1(B)), andsubjected to an electroless copper plating to form a power layer 4having a lattice-shaped conductor pattern (see FIG. 1(C)). The latticestructure of the power layer 4 is conductor width/resist width of 5mm/10 mm in an X-axis direction and conductor width/resist width=250μm/250 μm in a Y-axis direction.

Example 3

In this example, the power layer constituting the multilayer printedwiring board is formed as follows.

At first, an interlaminar insulating layer 2 made of a heat-resistantresin (PES-epoxy resin) is formed on a substrate 1 and the surface ofthe interlaminar insulating layer 2 is roughened with a solution ofpermanganate to a roughness of Rz=6 μm according to JIS-B0601 (see FIG.1(A)). Moreover, the interlaminar insulating layer 2 after theroughening has a thickness of 35 μm.

Then, a desired permanent resist (made of epoxy resin) 3 correspondingto the conductor pattern of the power layer is pattern-printed onto thesurface of the interlaminar insulating layer (see FIG. 1(B)), andsubjected to an electroless copper plating to form a power layer 4having a lattice-shaped conductor pattern (see FIG. 1(C)). The latticestructure of the power layer 4 is conductor width/resist width=250μm/250 μm in both directions of X-axis and Y-axis. In this case, each offour corners in each lattice face surrounded by the conductor pattern issubjected to a round treatment.

Comparative Example 1

In this comparative example, the power layer constituting the multilayerprinted wiring board is formed as follows.

At first, an interlaminar insulating layer 2 made of a heat-resistantresin (PES-epoxy resin) is formed on a substrate 1 and the surface ofthe interlaminar insulating layer 2 is roughened with a solution ofpermanganate to a roughness of Rz=6 μm according to JIS-B0601 (see FIG.2(A)). Moreover, the interlaminar insulating layer 2 after theroughening has a thickness of 35 μm.

Then, a desired permanent resist (made of epoxy resin) 3 correspondingto the conductor pattern of the power layer is pattern-printed onto thesurface of the interlaminar insulating layer (see FIG. 2(B)), andsubjected to an electroless copper plating to form a power layer 4having a flat pattern (see FIG. 2(C)). This flat pattern is a conductorpattern of a power layer 4 in the conventional multilayer printed wiringboard and its size is 20 mm□.

Comparative Example 2

In this comparative example, the power layer constituting the multilayerprinted wiring board is formed as follows.

At first, an interlaminar insulating layer 2 made of a heat-resistantresin (PES-epoxy resin) is formed on a substrate 1 and the surface ofthe interlaminar insulating layer 2 is roughened with a solution ofpermanganate to a roughness of Rz=6 μm according to JIS-B0601 (see FIG.2(A)). Moreover, the interlaminar insulating layer 2 after theroughening has a thickness of 35 μm.

Then, a desired permanent resist (made of epoxy resin) 3 correspondingto the conductor pattern of the power layer is pattern-printed onto thesurface of the interlaminar insulating layer (see FIG. 2(B)), andsubjected to an electroless copper plating to form a power layer 4having a lattice-shaped conductor pattern (see FIG. 2(C)). The latticestructure of the power layer 4 is conductor width/resist width of 50μm/50 μm in both directions of X-axis and Y-axis.

Comparative Example 3

In this comparative example, the power layer constituting the multilayerprinted wiring board is formed as follows.

At first, an interlaminar insulating layer 2 made of a heat-resistantresin (PES-epoxy resin) is formed on a substrate 1 and the surface ofthe interlaminar insulating layer 2 is roughened with a solution ofpermanganate to a roughness of Rz=6 μm according to JIS-B0601 (see FIG.2(A)). Moreover, the interlaminar insulating layer 2 after theroughening has a thickness of 35 μm.

Then, a desired permanent resist (made of epoxy resin) 3 correspondingto the conductor pattern of the power layer is pattern-printed onto thesurface of the interlaminar insulating layer (see FIG. 2(B)), andsubjected to an electroless copper plating to form a power layer 4having a lattice-shaped conductor pattern (see FIG. 2(C)). The latticestructure of the power layer 4 is conductor width/resist width of 10mm/300 μm in both directions of X-axis and Y-axis.

With respect to the thus formed power layers, tests for reliability suchas appearance observation, TCT test (test for resistance to cool-heatshock), test for adhesion strength and the like are carried out. Theresults are shown in Table 1.

TABLE 1 Conductor width/ distance between *1 *3 conductors (mm/mm)Swelling Test for X-axis Y-axis after *2 adhesion direction directionplating TCT test strength Example 1 0.25/0.25 0.25/0.25 none after 900cyc ◯ Example 2  5/10 0.25/0.25 none after 700 cyc ◯ Example 3 0.25/0.250.25/0.25 none more than ◯ 1000 cyc Compara- no lattice no latticepresence more than X tive 1000 cyc Example 1 Compara- 0.05/0.050.05/0.05 none after 800 cyc X tive Example 2 Compara-   15/0.30  15/0.30 presence after 800 cyc X tive Example 3 *1; presence orabsence of swelling after the plating; visual inspection is carried out.*2; TCT test: indicates a time of generating cracks in the resistthrough cool-heat cycle of −65° C. 125° C. *3; test for adhesionstrength: After the substrate is immersed in boiling water for 1 hour,it is immersed in a solder bath at 180° C. for 30 minutes, the presenceor absence of swelling produced between conductor layer and insulatinglayer is evaluated. ◯ ˜ none of swelling X ˜ presence of swelling

As seen from the results of this table, the power layer having thelattice-shaped conductor pattern according to the invention does notproduce the “swelling,” in the high-temperature treatment of subsequentstep (e.g., drying at the step of the plating treatment) because theresidual solvent in the resin layer beneath the conductor easily comesout. Also, when each corner of the cross portions in the lattice-shapedconductor pattern of the power layer is curved, the crack is notgenerated in the resist in the TCT test and the resistance to cool-heatshock is improved.

On the contrary, in the power layer having the flat pattern as shown inComparative Example 1, the “swelling” is observed in the hightemperature treatment of the subsequent step because the residualsolvent in the resin layer beneath the conductor does not completelycome out.

In the power layer having a lattice structure wherein both the conductorwidth and resist width are narrow as shown in Comparative Example 2, thedeveloped residue of the resist is easily caused in the portion formingthe conductor pattern because the resist pattern is fine, and theadhesion property to the interlaminar insulating layer beneath theconductor is poor. Also, the power layer shown in Comparative Example 2is required to be provided with a land having a width larger than thelattice distance (conductor width) on its portion tor connection fromthe upper layer or connection to the lower layer, so that the designbecomes complicated.

Further, in the power layer having such a lattice structure that theconductor width is wider than the preferable range of the invention asshown in Comparative Example 3, the residual solvent in the resin layerbeneath the conductor does not completely come out, so that the“swelling” is observed in the high temperature treatment of thesubsequent step.

What is claimed is:
 1. A multilayer printed wiring board comprising: asubstrate; at least one resin insulating layer and at least oneconductor layer laminated on said substrate; said at least one resininsulating layer comprising a roughened surface; said at least oneconductor layer comprising at least a signal layer and a power layer;and said power layer comprising a lattice-shaped conductor patternincluding a conductor width of about 100 μm to 5 mm, and a distance froma conductor edge to an opposing conductor edge of about 100 μm to 10 mm.2. The multilayer printed circuit wiring board according to claim 1,wherein each corner part in a cross portion of the lattice-shapedconductor pattern is curved.
 3. The multilayer printed circuit wiringboard according to claim 1, wherein the at least one resin insulatinglayer and said at least one conductor layer comprise a plurality ofinsulating layers and conductor layers.
 4. The multilayer printedcircuit wiring board according to claim 2, wherein the at least oneresin insulating layer and said at least one conductor layer comprise aplurality of insulating layers and conductor layers.